View S80L188EA13_7764531.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. october 1995 copyright ? intel corporation, 1995 order number: 272432-003 80c186ea/80c188ea and 80l186ea/80l188ea 16-bit high-integration embedded processors y 80c186 upgrade for power critical applications y fully static operation y true cmos inputs and outputs y integrated feature set e static 186 cpu core e power save, idle and powerdown modes e clock generator e 2 independent dma channels e 3 programmable 16-bit timers e dynamic ram refresh control unit e programmable memory and peripheral chip select logic e programmable wait state generator e local bus controller e system-level testing support (high impedance test mode) y speed versions available (5v): e 25 mhz (80c186ea25/80c188ea25) e 20 mhz (80c186ea20/80c188ea20) e 13 mhz (80c186ea13/80c188ea13) y speed versions available (3v): e 13 mhz (80l186ea13/80l188ea13) e 8 mhz (80l186ea8/80l188ea8) y direct addressing capability to 1 mbyte memory and 64 kbyte i/o y supports 80c187 numeric coprocessor interface (80c186ea only) y available in the following packages: e 68-pin plastic leaded chip carrier (plcc) e 80-pin eiaj quad flat pack (qfp) e 80-pin shrink quad flat pack (sqfp) y available in extended temperature range ( b 40 cto a 85 c) the 80c186ea is a chmos high integration embedded microprocessor. the 80c186ea includes all of the features of an ``enhanced mode'' 80c186 while adding the additional capabilities of idle and powerdown modes. in numerics mode, the 80c186ea interfaces directly with an 80c187 numerics coprocessor. 272432 1 1
80c186ea/80c188ea, 80l186ea/80l188ea 80c186ea/80c188ea and 80l186ea/80l188ea 16-bit high integration embedded processor contents page introduction 4 80c186ea core architecture 4 bus interface unit 4 clock generator 4 80c186ea peripheral architecture 5 interrupt control unit 5 timer/counter unit 5 dma control unit 7 chip-select unit 7 refresh control unit 7 power management 7 80c187 interface (80c186ea only) 8 once test mode 8 differences between the 80c186xl and the 80c186ea 8 pinout compatibility 8 operating modes 8 ttl vs cmos inputs 8 timing specifications 8 package information 9 prefix identification 9 pin descriptions 9 80c186ea pinout 15 contents page package thermal specifications 20 electrical specifications 21 absolute maximum ratings 21 recommended connections 21 dc specifications 22 i cc versus frequency and voltage 24 pdtmr pin delay calculation 24 ac specifications 25 ac characteristicse80c186ea20/13 25 ac characteristicse80l186ea13/8 27 relative timings 29 ac test conditions 30 ac timing waveforms 30 derating curves 33 reset 33 bus cycle waveforms 36 execution timings 43 instruction set summary 44 revision history 50 errata 50 2 2
80c186ea/80c188ea, 80l186ea/80l188ea note: pin names in parentheses apply to the 80c186ea/80l188ea figure 1. 80c186ea/80c188ea block diagram 272432 2 3 3
80c186ea/80c188ea, 80l186ea/80l188ea introduction unless specifically noted, all references to the 80c186ea apply to the 80c188ea, 80l186ea, and 80l188ea. references to pins that differ between the 80c186ea/80l186ea and the 80c188ea/ 80l188ea are given in parentheses. the ``l'' in the part number denotes low voltage operation. physi- cally and functionally, the ``c'' and ``l'' devices are identical. the 80c186ea is the second product in a new gen- eration of low-power, high-integration microproces- sors. it enhances the existing 80c186xl family by offering new features and operating modes. the 80c186ea is object code compatible with the 80c186xl embedded processor. the 80l186ea is the 3v version of the 80c186ea. the 80l186ea is functionally identical to the 80c186ea embedded processor. current 80c186ea customers can easily upgrade their de- signs to use the 80l186ea and benefit from the re- duced power consumption inherent in 3v operation. the feature set of the 80c186ea/80l186ea meets the needs of low-power, space-critical applications. low-power applications benefit from the static de- sign of the cpu core and the integrated peripherals as well as low voltage operation. minimum current consumption is achieved by providing a powerdown mode that halts operation of the device, and freezes the clock circuits. peripheral design enhancements ensure that non-initialized peripherals consume little current. space-critical applications benefit from the inte- gration of commonly used system peripherals. two flexible dma channels perform cpu-independent data transfers. a flexible chip select unit simplifies memory and peripheral interfacing. the interrupt unit provides sources for up to 128 external interrupts and will prioritize these interrupts with those generat- ed from the on-chip peripherals. three general pur- pose timer/counters round out the feature set of the 80c186ea. figure 1 shows a block diagram of the 80c186ea/ 80c188ea. the execution unit (eu) is an enhanced 8086 cpu core that includes: dedicated hardware to speed up effective address calculations, enhance execution speed for multiple-bit shift and rotate in- structions and for multiply and divide instructions, string move instructions that operate at full bus bandwidth, ten new instructions, and static opera- tion. the bus interface unit (biu) is the same as that found on the original 80c186 family products. an independent internal bus is used to allow communi- cation between the biu and internal peripherals. 80c186ea core architecture bus interface unit the 80c186ea core incorporates a bus controller that generates local bus control signals. in addition, it employs a hold/hlda protocol to share the local bus with other bus masters. the bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle status information and data (for write operations) in- formation. it is also responsible for reading data off the local bus during a read operation. srdy and ardy input pins are provided to extend a bus cycle beyond the minimum four states (clocks). the local bus controller also generates two control signals (den and dt/r ) when interfacing to exter- nal transceiver chips. this capability allows the addi- tion of transceivers for simple buffering of the mulit- plexed address/data bus. clock generator the processor provides an on-chip clock generator for both internal and external clock generation. the clock generator features a crystal oscillator, a divide- by-two counter, and two low-power operating modes. the oscillator circuit is designed to be used with ei- ther a parallel resonant fundamental or third-over- tone mode crystal network. alternatively, the oscilla- tor circuit may be driven from an external clock source. figure 2 shows the various operating modes of the oscillator circuit. the crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter. this counter is used to drive all internal phase clocks and the exter- nal clkout signal. clkout is a 50% duty cycle processor clock and can be used to drive other sys- tem components. all ac timings are referenced to clkout. the following parameters are recommended when choosing a crystal: temperature range: application specific esr (equivalent series resistance): 60 x max c0 (shunt capacitance of crystal): 7.0 pf max c l (load capacitance): 20 pf g 2pf drive level: 2 mw max 4 4
80c186ea/80c188ea, 80l186ea/80l188ea 272432 3 (a) crystal connection note: the l 1 c 1 network is only required when using a third-overtone crystal. 272432 4 (b) clock connection figure 2. clock configurations 80c186ea peripheral architecture the 80c186ea has integrated several common sys- tem peripherals with a cpu core to create a com- pact, yet powerful system. the integrated peripher- als are designed to be flexible and provide logical interconnections between supporting units (e.g., the interrupt control unit supports interrupt requests from the timer/counters or dma channels). the list of integrated peripherals include: # 4-input interrupt control unit # 3-channel timer/counter unit # 2-channel dma unit # 13-output chip-select unit # refresh control unit # power management logic the registers associated with each integrated peri- heral are contained within a 128 x 16 register file called the peripheral control block (pcb). the pcb can be located in either memory or i/o space on any 256 byte address boundary. figure 3 provides a list of the registers associated with the pcb when the processor's interrupt control unit is in master mode. in slave mode, the defini- tions of some registers change. figure 4 provides register definitions specific to slave mode. interrupt control unit the 80c186ea can receive interrupts from a num- ber of sources, both internal and external. the inter- rupt control unit (icu) serves to merge these re- quests on a priority basis, for individual service by the cpu. each interrupt source can be independent- ly masked by the interrupt control unit or all inter- rupts can be globally masked by the cpu. internal interrupt sources include the timers and dma channels. external interrupt sources come from the four input pins int3:0. the nmi interrupt pin is not controlled by the icu and is passed direct- ly to the cpu. although the timers only have one request input to the icu, separate vector types are generated to service individual interrupts within the timer unit. timer/counter unit the 80c186ea timer/counter unit (tcu) provides three 16-bit programmable timers. two of these are highly flexible and are connected to external pins for control or clocking. a third timer is not connected to any external pins and can only be clocked internally. however, it can be used to clock the other two timer channels. the tcu can be used to count external events, time external events, generate non-repeti- tive waveforms, generate timed interrupts, etc. 5 5
80c186ea/80c188ea, 80l186ea/80l188ea pcb function offset 00h reserved 02h reserved 04h reserved 06h reserved 08h reserved 0ah reserved 0ch reserved 0eh reserved 10h reserved 12h reserved 14h reserved 16h reserved 18h reserved 1ah reserved 1ch reserved 1eh reserved 20h reserved 22h end of interrupt 24h poll 26h poll status 28h interrupt mask 2ah priority mask 2ch in-service 2eh interrupt request 30h interrupt status 32h timer control 34h dma0 int. control 36h dma1 int. control 38h int0 control 3ah int1 control 3ch int2 control 3eh int3 control pcb function offset 40h reserved 42h reserved 44h reserved 46h reserved 48h reserved 4ah reserved 4ch reserved 4eh reserved 50h timer 0 count 52h timer 0 compare a 54h timer 0 compare b 56h timer 0 control 58h timer 1 count 5ah timer 1 compare a 5ch timer 1 compare b 5eh timer 1 control 60h timer 2 count 62h timer 2 compare 64h reserved 66h timer 2 control 68h reserved 6ah reserved 6ch reserved 6eh reserved 70h reserved 72h reserved 74h reserved 76h reserved 78h reserved 7ah reserved 7ch reserved 7eh reserved pcb function offset 80h reserved 82h reserved 84h reserved 86h reserved 88h reserved 8ah reserved 8ch reserved 8eh reserved 90h reserved 92h reserved 94h reserved 96h reserved 98h reserved 9ah reserved 9ch reserved 9eh reserved a0h umcs a2h lmcs a4h pacs a6h mmcs a8h mpcs aah reserved ach reserved aeh reserved b0h reserved b2h reserved b4h reserved b6h reserved b8h reserved bah reserved bch reserved beh reserved pcb function offset c0h dma0 src. lo c2h dma0 src. hi c4h dma0 dest. lo c6h dma0 dest. hi c8h dma0 count cah dma0 control cch reserved ceh reserved d0h dma1 src. lo d2h dma1 src. hi d4h dma1 dest. lo d6h dma1 dest. hi d8h dma1 count dah dma1 control dch reserved deh reserved e0h refresh base e2h refresh time e4h refresh control e6h reserved e8h reserved eah reserved ech reserved eeh reserved f0h power-save f2h power control f4h reserved f6h step id f8h reserved fah reserved fch reserved feh relocation figure 3. peripheral control block registers 6 6
80c186ea/80c188ea, 80l186ea/80l188ea pcb function offset 20h interrupt vector 22h specific eoi 24h reserved 26h reserved 28h interrupt mask 2ah priority mask 2c in-service 2e interrupt request 30 interrupt status 32 tmr0 interrupt control 34 dma0 interrupt control 36 dma1 interrupt control 38 tmr1 interrupt control 3a tmr2 interrupt control 3c reserved 3e reserved figure 4. 80c186ea slave mode peripheral control block registers dma control unit the 80c186ea dma contol unit provides two inde- pendent high-speed dma channels. data transfers can occur between memory and i/o space in any combination: memory to memory, memory to i/o, i/o to i/o or i/o to memory. data can be trans- ferred either in bytes or words. transfers may pro- ceed to or from either even or odd addresses, but even-aligned word transfers proceed at a faster rate. each data transfer consumes two bus cycles (a mini- mum of eight clocks), one cycle to fetch data and the other to store data. the chip-select/ready logic may be programmed to point to the memory or i/o space subject to dma transfers in order to provide hardware chip select lines. dma cycles run at higher priority than general processor execution cycles. chip-select unit the 80c186ea chip-select unit integrates logic which provides up to 13 programmable chip-selects to access both memories and peripherals. in addi- tion, each chip-select can be programmed to auto- matically terminate a bus cycle independent of the condition of the srdy and ardy input pins. the chip-select lines are available for all memory and i/o bus cycles, whether they are generated by the cpu, the dma unit, or the refresh control unit. refresh control unit the refresh control unit (rcu) automatically gen- erates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed. a 9-bit counter controls the number of clocks between re- fresh requests. a 9-bit address generator is maintained by the rcu with the address presented on the a9:1 address lines during the refresh bus cycle. address bits a19:13 are programmable to allow the refresh ad- dress block to be located on any 8 kbyte boundary. power management the 80c186ea has three operational modes to con- trol the power consumption of the device. they are power save mode, idle mode, and powerdown mode. power save mode divides the processor clock by a programmable value to take advantage of the fact that current is linearly proportional to frequency. an unmasked interrupt, nmi, or reset will cause the 80c186ea to exit power save mode. idle mode freezes the clocks of the execution unit and the bus interface unit at a logic zero state while all peripherals operate normally. powerdown mode freezes all internal clocks at a logic zero level and disables the crystal oscillator. all internal registers hold their values provided v cc is maintained. current consumption is reduced to tran- sistor leakage only. 7 7
80c186ea/80c188ea, 80l186ea/80l188ea 80c187 interface (80c186ea only) the 80c187 numerics coprocessor may be used to extend the 80c186ea instruction set to include floating point and advanced integer instructions. connecting the 80c186ea resout and test / busy pins to the 80c187 enables numerics mode operation. in numerics mode, three of the four mid- range chip select (mcs ) pins become handshaking pins for the interface. the exchange of data and control information proceeds through four dedicated i/o ports. if an 80c187 is not present, the 80c186ea config- ures itself for regular operation at reset. note: the 80c187 is not specified for 3v operation and therefore does not interface directly to the 80l186ea. once test mode to facilitate testing and inspection of devices when fixed into a target system, the 80c186ea has a test mode available which forces all output and input/ output pins to be placed in the high-impedance state. once stands for ``on circuit emulation''. the once mode is selected by forcing the ucs and lcs pins low (0) during a processor reset (these pins are weakly held to a high (1) level) while resin is active. differences between the 80c186xl and the 80c186ea the 80c186ea is intended as a direct functional up- grade for 80c186xl designs. in many cases, it will be possible to replace an existing 80c186xl with little or no hardware redesign. the following sections describe differences in pinout, operating modes, and ac and dc specifications to keep in mind. pinout compatibility the 80c186ea requires a pdtmr pin to time the processor's exit from powerdown mode. the original pin arrangement for the 80c186xl in the plcc package did not have any spare leads to use for pdtmr, so the dt/r pin was sacrificed. the ar- rangement of all the other leads in the 68-lead plcc is identical between the 80c186xl and the 80c186ea. dt/r may be synthesized by latching the s1 status output. therefore, upgrading a plcc 80c186xl to plcc 80c186ea is straightforward. the 80-lead qfp (eiaj) pinouts are different be- tween the 80c186xl and the 80c186ea. in addition to the pdtmr pin, the 80c186ea has more power and ground pins and the overall arrangement of pins was shifted. a new circuit board layout for the 80c186ea is required. operating modes the 80c186xl has two operating modes, compati- ble and enhanced. compatible mode is a pin-to-pin replacement for the nmos 80186, except for nu- merics coprocessing. in enhanced mode, the proc- essor has a refresh control unit, the power-save feature and an interface to the 80c187 numerics coprocessor. the mcs0 , mcs1 , and mcs3 pins change their functions to constitute handshaking pins for the 80c187. the 80c186ea allows all non-80c187 users to use all the mcs pins for chip-selects. in regular opera- tion, all 80c186ea features (including those of the enhanced mode 80c186) are present except for the interface to the 80c187. numerics mode disables the three chip-select pins and reconfigures them for connection to the 80c187. ttl vs cmos inputs the inputs of the 80c186ea are rated for cmos switching levels for improved noise immunity, but the 80c186xl inputs are rated for ttl switching levels. in particular, the 80c186ea requires a minimum v ih of 3.5v to recognize a logic one while the 80c186xl requires a minimum v ih of only 1.9v (assuming 5.0v operation). the solution is to drive the 80c186ea with true cmos devices, such as those from the hc and ac logic families, or to use pullup resistors where the added current draw is not a problem. timing specifications 80c186ea timing relationships are expressed in a simplified format over the 80c186xl. the ac per- formance of an 80c186ea at a specified frequency will be very close to that of an 80c186xl at the same frequency. check the timings applicable to your design prior to replacing the 80c186xl. 8 8
80c186ea/80c188ea, 80l186ea/80l188ea package information this section describes the pins, pinouts, and thermal characteristics for the 80c186ea in the plastic leaded chip carrier (plcc) package, shrink quad flat pack (sqfp), and quad flat pack (qfp) pack- age. for complete package specifications and infor- mation, see the intel packaging outlines and dimen- sions guide (order number: 231369). with the extended temperature range operational characteristics are guaranteed over a temperature range corresponding to b 40 cto a 85 c ambient. package types are identified by a two-letter prefix to the part number. the prefixes are listed in table 1. table 1. prefix identification prefix note package temperature type range tn plcc extended ts qfp (eiaj) extended sb 1 sqfp extended/commercial n 1 plcc commercial s 1 qfp (eiaj) commercial note: 1. the 25 mhz version is only available in commercial tem- perature range corresponding to 0 cto a 70 c ambient. pin descriptions each pin or logical set of pins is described in table 3. there are three columns for each entry in the pin description table. the pin name column contains a mnemonic that describes the pin function. negation of the signal name (for example, resin ) denotes a signal that is active low. the pin type column contains two kinds of informa- tion. the first symbol indicates whether a pin is pow- er (p), ground (g), input only (i), output only (o) or input/output (i/o). some pins have multiplexed functions (for example, a19/s6). additional symbols indicate additional characteristics for each pin. table 3 lists all the possible symbols for this column. the input type column indicates the type of input (asynchronous or synchronous). asynchronous pins require that setup and hold times be met only in order to guarantee recognition at a particular clock edge. synchronous pins require that setup and hold times be met to guarantee proper operation. for example, missing the setup or hold time for the srdy pin (a synchronous input) will re- sult in a system failure or lockup. input pins may also be edge- or level-sensitive. the possible character- istics for input pins are s(e), s(l), a(e) and a(l). the output states column indicates the output state as a function of the device operating mode. output states are dependent upon the current activi- ty of the processor. there are four operational states that are different from regular operation: bus hold, reset, idle mode and powerdown mode. ap- propriate characteristics for these states are also in- dicated in this column, with the legend for all possi- ble characteristics in table 2. the pin description column contains a text de- scription of each pin. as an example, consider ad15:0. i/o signifies the pins are bidirectional. s(l) signifies that the input function is synchronous and level-sensitive. h(z) signifies that, as outputs, the pins are high-imped- ance upon acknowledgement of bus hold. r(z) sig- nifies that the pins float during reset. p(x) signifies that the pins retain their states during powerdown mode. 9 9
80c186ea/80c188ea, 80l186ea/80l188ea table 2. pin description nomenclature symbol description p power pin (apply a v cc voltage) g ground (connect to v ss ) i input only pin o output only pin i/o input/output pin s(e) synchronous, edge sensitive s(l) synchronous, level sensitive a(e) asynchronous, edge sensitive a(l) asynchronous, level sensitive h(1) output driven to v cc during bus hold h(0) output driven to v ss during bus hold h(z) output floats during bus hold h(q) output remains active during bus hold h(x) output retains current state during bus hold r(wh) output weakly held at v cc during reset r(1) output driven to v cc during reset r(0) output driven to v ss during reset r(z) output floats during reset r(q) output remains active during reset r(x) output retains current state during reset i(1) output driven to v cc during idle mode i(0) output driven to v ss during idle mode i(z) output floats during idle mode i(q) output remains active during idle mode i(x) output retains current state during idle mode p(1) output driven to v cc during powerdown mode p(0) output driven to v ss during powerdown mode p(z) output floats during powerdown mode p(q) output remains active during powerdown mode p(x) output retains current state during powerdown mode 10 10
80c186ea/80c188ea, 80l186ea/80l188ea table 3. pin descriptions pin pin input output description name type type states v cc p power connections consist of six pins which must be shorted externally to a v cc board plane. v ss g ground connections consist of five pins which must be shorted externally to a v ss board plane. clkin i a(e) clock input is an input for an external clock. an external oscillator operating at two times the required processor operating frequency can be connected to clkin. for crystal operation, clkin (along with oscout) are the crystal connections to an internal pierce oscillator. oscout o h(q) oscillator output is only used when using a crystal to generate the external clock. oscout (along with clkin) are the crystal r(q) connections to an internal pierce oscillator. this pin is not to be p(q) used as 2x clock output for non-crystal applications (i.e., this pin is n.c. for non-crystal applications). oscout does not float in once mode. clkout o h(q) clock output provides a timing reference for inputs and outputs of the processor, and is one-half the input clock (clkin) r(q) frequency. clkout has a 50% duty cycle and transistions every p(q) falling edge of clkin. resin i a(l) reset in causes the processor to immediately terminate any bus cycle in progress and assume an initialized state. all pins will be driven to a known state, and resout will also be driven active. the rising edge (low-to-high) transition synchronizes clkout with clkin before the processor begins fetching opcodes at memory location 0ffff0h. resout o h(0) reset output that indicates the processor is currently in the reset state. resout will remain active as long as resin remains r(1) active. when tied to the test /busy pin, resout forces the p(0) 80c186ea into numerics mode. pdtmr i/o a(l) h(wh) power-down timer pin (normally connected to an external capacitor) that determines the amount of time the processor waits r(z) after an exit from power down before resuming normal operation. p(1) the duration of time required will depend on the startup characteristics of the crystal oscillator. nmi i a(e) non-maskable interrupt input causes a type 2 interrupt to be serviced by the cpu. nmi is latched internally. test /busy i a(e) test /busy is sampled upon reset to determine whether the 80c186ea is to enter numerics mode. in regular operation, the pin (test ) is test . test is used during the execution of the wait instruction to suspend cpu operation until the pin is sampled active (low). in numerics mode, the pin is busy . busy notifies the 80c186ea of 80c187 numerics coprocessor activity. ad15:0 i/o s(l) h(z) these pins provide a multiplexed address and data bus. during the address phase of the bus cycle, address bits 0 through 15 (0 (ad7:0) r(z) through 7 on the 8-bit bus versions) are presented on the bus and p(x) can be latched using ale. 8- or 16-bit data information is transferred during the data phase of the bus cycle. note: pin names in parentheses apply to the 80c188ea and 80l188ea. 11 11
80c186ea/80c188ea, 80l186ea/80l188ea table 3. pin descriptions (continued) pin pin input output description name type type states a18:16 o h(z) these pins provide multiplexed address during the address phase of the bus cycle. address bits 16 through 19 are a19/s6 a16 r(z) presented on these pins and can be latched using ale. (a19 a8) p(x) a18:16 are driven to a logic 0 during the data phase of the bus cycle. on the 8-bit bus versions, a15 a8 provide valid address information for the entire bus cycle. also during the data phase, s6 is driven to a logic 0 to indicate a cpu-initiated bus cycle or logic 1 to indicate a dma-initiated bus cycle or a refresh cycle. s2:0 o h(z) bus cycle status are encoded on these pins to provide bus transaction information. s2:0 are encoded as follows: r(z) p(1) s2 s1 s0 bus cycle initiated 0 0 0 interrupt acknowledge 0 0 1 read i/o 0 1 0 write i/o 0 1 1 processor halt 1 0 0 queue instruction fetch 1 0 1 read memory 1 1 0 write memory 1 1 1 passive (no bus activity) ale/qs0 o h(0) address latch enable output is used to strobe address information into a transparent type latch during the address r(0) phase of the bus cycle. in queue status mode, qs0 provides p(0) queue status information along with qs1. bhe o h(z) byte high enable output to indicate that the bus cycle in progress is transferring data over the upper half of the data (rfsh ) r(z) bus. bhe and a0 have the following logical encoding: p(x) a0 bhe encoding (for 80c186ea/80l186ea only) 0 0 word transfer 0 1 even byte transfer 1 0 odd byte transfer 1 1 refresh operation on the 80c188ea/80l188ea, rfsh is asserted low to indicate a refresh bus cycle. rd /qsmd o h(z) read output signals that the accessed memory or i/o device must drive data information onto the data bus. upon reset, this r(wh) pin has an alternate function. as qsmd , it enables queue p(1) status mode when grounded. in queue status mode, the ale/qs0 and wr /qs1 pins provide the following information about processor/instruction queue interaction: qs1 qs0 queue operation 0 0 no queue operation 0 1 first opcode byte fetched from the queue 1 1 subsequent byte fetched from the queue 1 0 empty the queue note: pin names in parentheses apply to the 80c188ea and 80l188ea. 12 12
80c186ea/80c188ea, 80l186ea/80l188ea table 3. pin descriptions (continued) pin pin input output description name type type states wr /qs1 o h(z) write output signals that data available on the data bus are to be written into the accessed memory or i/o device. in queue status r(z) mode, qs1 provides queue status information along with qs0. p(1) ardy i a(l) asychronous ready is an input to signal for the end of a bus cycle. ardy is asynchronous on rising clkout and synchronous on falling s(l) clkout. ardy or srdy must be active to terminate any processor bus cycle, unless they are ignored due to correct programming of the chip select unit. srdy i s(l) synchronous ready is an input to signal for the end of a bus cycle. ardy or srdy must be active to terminate any processor bus cycle, unless they are ignored due to correct programming of the chip select unit. den o h(z) data enable output to control the enable of bidirectional transceivers when buffering a system. den is active only when data is to be r(z) transferred on the bus. p(1) dt/r o h(z) data transmit/receive output controls the direction of a bi- directional buffer in a buffered system. dt/r is only available on the r(z) qfp (eiaj) package and the sqfp package. p(x) lock o h(z) lock output indicates that the bus cycle in progress is not to be interrupted. the processor will not service other bus requests (such r(wh) as hold) while lock is active. this pin is configured as a weakly p(1) held high input while resin is active and must not be driven low. hold i a(l) hold request input to signal that an external bus master wishes to gain control of the local bus. the processor will relinquish control of the local bus between instruction boundaries not conditioned by a lock prefix. hlda o h(1) hold acknowledge output to indicate that the processor has relinquished control of the local bus. when hlda is asserted, the r(0) processor will (or has) floated its data bus and control signals allowing p(0) another bus master to drive the signals directly. ucs o h(1) upper chip select will go active whenever the address of a memory or i/o bus cycle is within the address limitations programmed by the r(1) user. after reset, ucs is configured to be active for memory accesses p(1) between 0ffc00h and 0fffffh. during a processor reset, ucs and lcs are used to enable once mode. lcs o h(1) lower chip select will go active whenever the address of a memory bus cycle is within the address limitations programmed by the user. r(1) lcs is inactive after a reset. during a processor reset, ucs and lcs p(1) are used to enable once mode. note: pin names in parentheses apply to the 80c188ea and 80l188ea. 13 13
80c186ea/80c188ea, 80l186ea/80l188ea table 3. pin descriptions (continued) pin pin input output description name type type states mcs0 /pereq i/o a(l) h(1) these pins provide a multiplexed function. if enabled, these pins normally comprise a block of mid-range chip mcs1 /error r(1) select outputs which will go active whenever the address mcs2 p(1) of a memory bus cycle is within the address limitations mcs3 /ncs programmed by the user. in numerics mode (80c186ea only), three of the pins become handshaking pins for the 80c187. the coprocessor request input signals that a data transfer is pending. error is an input which indicates that the previous numerics coprocessor operation resulted in an exception condition. an interrupt type 16 is generated when error is sampled active at the beginning of a numerics operation. numerics coprocessor select is an output signal generated when the processor accesses the 80c187. pcs4:0 o h(1) peripheral chip selects go active whenever the address of a memory or i/o bus cycle is within the address r(1) limitations programmed by the user. p(1) pcs5 /a1 o h(1)/h(x) these pins provide a multiplexed function. as additional peripheral chip selects, they go active whenever the pcs6 /a2 r(1) address of a memory or i/o bus cycle is within the p(1) address limitations by the user. they may also be programmed to provide latched address a2:1 signals. t0out o h(q) timer output pins can be programmed to provide a single clock or continuous waveform generation, t1out r(1) depending on the timer mode selected. p(q) t0in i a(l) timer input is used either as clock or control signals, depending on the timer mode selected. t1in a(e) drq0 i a(l) dma request is asserted by an external request when it is prepared for a dma transfer. drq1 int0 i a(e,l) maskable interrupt input will cause a vector to a specific type interrupt routine. to allow interrupt expansion, int0 int1/select and/or int1 can be used with inta0 and inta1 to interface with an external slave controller. int1 becomes select when the icu is configured for slave mode. int2/inta0 i/o a(e,l) h(1) these pins provide multiplexed functions. as inputs, they provide a maskable interrupt that will cause the cpu to int3/inta1 /irq r(z) vector to a specific type interrupt routine. as outputs, p(1) each is programmatically controlled to provide an interrupt acknowledge handshake signal to allow interrupt expansion. int3/inta1 becomes irq when the icu is configured for slave mode. n.c. no connect. for compatibility with future products, do not connect to these pins. note: pin names in parentheses apply to the 80c188ea and 80l188ea. 14 14
80c186ea/80c188ea, 80l186ea/80l188ea 80c186ea pinout tables 4 and 5 list the 80c186ea pin names with package location for the 68-pin plastic leaded chip carrier (plcc) component. figure 9 depicts the complete 80c186ea/80l186ea pinout (plcc pack- age) as viewed from the top side of the component (i.e., contacts facing down). tables 6 and 7 list the 80c186ea pin names with package location for the 80-pin quad flat pack (eiaj) component. figure 6 depicts the complete 80c186ea/80c188ea (eiaj qfp package) as viewed from the top side of the component (i.e., con- tacts facing down). tables 8 and 9 list the 80c186ea/80c188ea pin names with package location for the 80-pin shrink quad flat pack (sqfp) component. figure 7 depicts the complete 80c186ea/80c188ea (sqfp) as viewed from the top side of the component (i.e., con- tacts facing down). table 4. plcc pin names with package location address/data bus name location ad0 17 ad1 15 ad2 13 ad3 11 ad4 8 ad5 6 ad6 4 ad7 2 ad8 (a8) 16 ad9 (a9) 14 ad10 (a10) 12 ad11 (a11) 10 ad12 (a12) 7 ad13 (a13) 5 ad14 (a14) 3 ad15 (a15) 1 a16 68 a17 67 a18 66 a19/s6 65 bus control name location ale/qs0 61 bhe (rfsh )64 s0 52 s1 53 s2 54 rd /qsmd 62 wr /qs1 63 ardy 55 srdy 49 den 39 lock 48 hold 50 hlda 51 power name location v ss 26, 60 v cc 9, 43 processor control name location resin 24 resout 57 clkin 59 oscout 58 clkout 56 test /busy 47 pdtmr 40 nmi 46 int0 45 int1/select 44 int2/inta0 42 int3/inta1 /41 irq i/o name location ucs 34 lcs 33 mcs0 /pereq 38 mcs1 /error 37 mcs2 36 mcs3 /ncs 35 pcs0 25 pcs1 27 pcs2 28 pcs3 29 pcs4 30 pcs5 /a1 31 pcs6 /a2 32 t0out 22 t0in 20 t1out 23 t1in 21 drq0 18 drq1 19 note: pin names in parentheses apply to the 80c188ea/80l188ea. 15 15
80c186ea/80c188ea, 80l186ea/80l188ea table 5. plcc package location with pin names location name 1 ad15 (a15) 2 ad7 3 ad14 (a14) 4 ad6 5 ad13 (a13) 6 ad5 7 ad12 (a12) 8 ad4 9v cc 10 ad11 (a11) 11 ad3 12 ad10 (a10) 13 ad2 14 ad9 (a9) 15 ad1 16 ad8 (a8) 17 ad0 location name 18 drq0 19 drq1 20 t0in 21 t1in 22 t0out 23 t1out 24 resin 25 pcs0 26 v ss 27 pcs1 28 pcs2 29 pcs3 30 pcs4 31 pcs5 /a1 32 pcs6 /a2 33 lcs 34 ucs location name 35 mcs3 /ncs 36 mcs2 37 mcs1 /error 38 mcs0 /pereq 39 den 40 pdtmr 41 int3/inta1 / irq 42 int2/inta0 43 v cc 44 int1/select 45 int0 46 nmi 47 test /busy 48 lock 49 srdy 50 hold 51 hlda location name 52 s0 53 s1 54 s2 55 ardy 56 clkout 57 resout 58 oscout 59 clkin 60 v ss 61 ale/qs0 62 rd /qsmd 63 wr /qs1 64 bhe (rfsh ) 65 a19/s6 66 a18 67 a17 68 a16 note: pin names in parentheses apply to the 80c186ea/80l188ea. notes: 272432 5 1. the nine-character alphanumeric code (xxxxxxxxd) underneath the product number is the intel fpo number. 2. pin names in parentheses apply to the 80c186ea/80l188ea. figure 5. 68-lead plcc pinout diagram 16 16
80c186ea/80c188ea, 80l186ea/80l188ea table 6. qfp (eiaj) pin names with package location address/data bus bus control processor control i/o name location name location name location name location ad0 64 ale/qs0 10 resin 55 ucs 45 ad1 66 bhe (rfsh ) 7 resout 18 lcs 46 ad2 68 s0 23 clkin 16 mcs0 /pereq 40 ad3 70 s1 22 oscout 17 mcs1 /error 41 ad4 74 s2 21 clkout 19 mcs2 42 ad5 76 rd /qsmd 9 test /busy 29 mcs3 /ncs 43 ad6 78 wr /qs1 8 pdtmr 38 pcs0 54 ad7 80 ardy 20 nmi 30 pcs1 52 ad8 (a8) 65 srdy 27 int0 31 pcs2 51 ad9 (a9) 67 dt/r 37 int1/select 32 pcs3 50 ad10 (a10) 69 den 39 int2/inta0 35 pcs4 49 ad11 (a11) 71 lock 28 int3/inta1 / 36 pcs5 /a1 48 ad12 (a12) 75 hold 26 irq pcs6 /a2 47 ad13 (a13) 77 hlda 25 n.c. 11, 14, t0out 57 ad14 (a14) 79 15, 63 t0in 59 ad15 (a15) 1 t1out 56 a16 3 power t1in 58 a17 4 name location drq0 61 a18 5 v ss 12, 13, 24, drq1 60 a19/s6 6 53,62 v cc 2, 33, 34, 44, 72, 73 note: pin names in parentheses apply to the 80c186ea/80l188ea. 17 17
80c186ea/80c188ea, 80l186ea/80l188ea table 7. qfp (eiaj) package location with pin names location name location name location name location name 1 ad15 (a15) 21 s2 41 mcs1 /error 61 drq0 2v cc 22 s1 42 mcs2 62 v ss 3 a16 23 s0 43 mcs3 /ncs 63 n.c. 4 a17 24 v ss 44 v cc 64 ad0 5 a18 25 hlda 45 ucs 65 ad8 (a8) 6 a19/s6 26 hold 46 lcs 66 ad1 7 bhe (rfsh ) 27 srdy 47 pcs6 /a2 67 ad9 (a9) 8wr /qs1 28 lock 48 pcs5 /a1 68 ad2 9rd /qsmd 29 test /busy 49 pcs4 69 ad10 (a10) 10 ale/qs0 30 nmi 50 pcs3 70 ad3 11 n.c. 31 int0 51 pcs2 71 ad11 (a11) 12 v ss 32 int1/select 52 pcs1 72 v cc 13 v ss 33 v cc 53 v ss 73 v cc 14 n.c. 34 v cc 54 pcs0 74 ad4 15 n.c. 35 int2/inta0 55 resin 75 ad12 (a12) 16 clkin 36 int3/inta1 / 56 t1out 76 ad5 17 oscout irq 57 t0out 77 ad13 (a13) 18 resout 37 dt/r 58 t1in 78 ad6 19 clkout 38 pdtmr 59 t0in 79 ad14 (a14) 20 ardy 39 den 60 drq1 80 ad7 40 mcs0 /pereq note: pin names in parentheses apply to the 80c186ea/80l188ea. notes: 272432 6 1. the nine-character alphanumeric code (xxxxxxxxd) underneath the product number is the intel fpo number. 2. pin names in parentheses apply to the 80c186ea/80l188ea. figure 6. quad flat pack (eiaj) pinout diagram 18 18
80c186ea/80c188ea, 80l186ea/80l188ea table 8. sqfp pin functions with package location ad bus ad0 1 ad1 3 ad2 6 ad3 8 ad4 12 ad5 14 ad6 16 ad7 18 ad8 (a8) 2 ad9 (a9) 5 ad10 (a10) 7 ad11 (a11) 9 ad12 (a12) 13 ad13 (a13) 15 ad14 (a14) 17 ad15 (a15) 19 a16/s3 21 a17/s4 22 a18/s5 23 a19/s6 24 bus control ale/qs0 29 bhe /(rfsh )26 s0 40 s1 39 s2 38 rd /qsmd 28 wr /qs1 27 ardy 37 srdy 44 den 56 dt/r 54 lock 45 hold 43 hlda 42 no connection n.c. 4 n.c. 25 n.c. 35 n.c. 72 processor control resin 73 resout 34 clkin 32 oscout 33 clkout 36 test /busy 46 nmi 47 int0 48 int1/select 49 int2/inta0 52 int3/inta1 53 pdtmr 55 power and ground v cc 10 v cc 11 v cc 20 v cc 50 v cc 51 v cc 61 v ss 30 v ss 31 v ss 41 v ss 70 v ss 80 i/o ucs 62 lcs 63 mcs0 /pereq 57 mcs1 /error 58 mcs2 59 mcs3 /nps 60 pcs0 71 pcs1 69 pcs2 68 pcs3 67 pcs4 66 pcs5 /a1 65 pcs6 /a2 64 tmr in 0 77 tmr in 1 76 tmr out 0 75 tmr out 1 74 drq0 79 drq1 78 note: pin names in parentheses apply to the 80c186ea/80l188ea. table 9. sqfp pin locations with pin names 1 ad0 2 ad8 (a8) 3 ad1 4 n.c. 5 ad9 (a9) 6 ad2 7 ad10 (a10) 8 ad3 9 ad11 (a11) 10 v cc 11 v cc 12 ad4 13 ad12 (a12) 14 ad5 15 ad13 (a13) 16 ad6 17 ad14 (a14) 18 ad7 19 ad15 (a15) 20 v cc 21 a16/s3 22 a17/s4 23 a18/s5 24 a19/s6 25 n.c. 26 bhe /(rfsh ) 27 wr /qs1 28 rd/qsmd 29 ale/qs0 30 v ss 31 v ss 32 x1 33 x2 34 reset 35 n.c. 36 clkout 37 ardy 38 s2 39 s1 40 s0 41 v ss 42 hlda 43 hold 44 srdy 45 lock 46 test /busy 47 nmi 48 int0 49 int1/select 50 v cc 51 v cc 52 int2/inta0 53 int3/inta1 54 dt/r 55 pdtmr 56 den 57 mcs0 /pereq 58 mcs1 /error 59 mcs2 60 mcs3 /nps 61 v cc 62 ucs 63 lcs 64 pcs6 /a2 65 pcs5 /a1 66 pcs4 67 pcs3 68 pcs2 69 pcs1 70 v ss 71 pcs0 72 n.c. 73 res 74 tmr out 1 75 tmr out 0 76 tmr in 1 77 tmr in 0 78 drq1 79 drq0 80 v ss note: pin names in parentheses apply to the 80c186ea/80l188ea. 19 19
80c186ea/80c188ea, 80l186ea/80l188ea 272432 7 figure 7. shrink quad flat pack (sqfp) pinout diagram notes: 1. xxxxxxxxd indicates the intel fpo number. 2. pin names in parentheses apply to the 80c188ea. package thermal specifications the 80c186ea/80l186ea is specified for operation when t c (the case temperature) is within the range of 0 cto85 c (plcc package) or 0 cto106 c (qfp-eiaj) package. t c may be measured in any environment to determine whether the processor is within the specified operating range. the case tem- perature must be measured at the center of the top surface. t a (the ambient temperature) can be calculated from i ca (thermal resistance from the case to ambi- ent) with the following equation: t a e t c -p c i ca typical values for i ca at various airflows are given in table 10. p (the maximum power consumption, specified in watts) is calculated by using the maximum icc as tabulated in the dc specifications and v cc of 5.5v. table 10. thermal resistance ( i ca ) at various airflows (in c/watt) airflow linear ft/min (m/sec) 0 200 400 600 800 1000 (0) (1.01) (2.03) (3.04) (4.06) (5.07) i ca (plcc) 29 25 21 19 17 16.5 i ca (qfp) 66 63 60.5 59 58 57 i ca (sqfp) 70 20 20
80c186ea/80c188ea, 80l186ea/80l188ea electrical specifications absolute maximum ratings * storage temperature b 65 cto a 150 c case temperature under bias b 65 cto a 150 c supply voltage with respect to v ss b 0.5v to a 6.5v voltage on other pins with respect to v ss b 0.5v to v cc a 0.5v notice: this data sheet contains preliminary infor- mation on new products in production. it is valid for the devices indicated in the revision history. the specifications are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. recommended connections power and ground connections must be made to multiple v cc and v ss pins. every 80c186ea based circuit board should contain separate power (v cc ) and ground (v ss ) planes. all v cc and v ss pins must be connected to the appropriate plane. pins identi- fied as ``n.c.'' must not be connected in the system. decoupling capacitors should be placed near the processor. the value and type of decoupling capac- itors is application and board layout dependent. the processor can cause transient power surges when its output buffers transition, particularly when con- nected to large capacitive loads. always connect any unused input pins to an appro- priate signal level. in particular, unused interrupt pins (nmi, int3:0) should be connected to v ss to avoid unwanted interrupts. leave any unused output pin or any ``n.c.'' pin unconnected. 21 21
80c186ea/80c188ea, 80l186ea/80l188ea dc specifications (80c186ea/80c188ea) symbol parameter min max units conditions v cc supply voltage 4.5 5.5 v v il input low voltage for all pins b 0.5 0.3 v cc v v ih input high voltage for all pins 0.7 v cc v cc a 0.5 v v ol output low voltage 0.45 v i ol e 3 ma (min) v oh output high voltage v cc b 0.5 v i oh eb 2 ma (min) v hyr input hysterisis on resin 0.30 v i il1 input leakage current (except g 10 m a0v s v in s v cc rd /qsmd , ucs , lcs , mcs0 /pereq, mcs1 /error , lock and test /busy) i il2 input leakage current b 275 m av in e 0.7 v cc (rd /qsmd , ucs , lcs , mcs0 /pereq, (note 1) mcs1 , error , lock and test /busy i ol output leakage current g 10 m a 0.45 s v out s v cc (note 2) i cc supply current cold (reset) 80c186ea25/80c188ea25 105 ma (notes 3, 5) 80c186ea20/80c188ea20 90 ma 80c186ea13/80c188ea13 65 ma i id supply current in idle mode 80c186ea25/80c188ea25 90 ma (note 5) 80c186ea20/80c188ea20 70 ma 80c186ea13/80c188ea13 46 ma i pd supply current in powerdown mode 80c186ea25/80c188ea25 100 m a (note 5) 80c186ea20/80c188ea20 100 m a 80c186ea13/80c188ea13 100 m a c out output pin capacitance 0 15 pf t f e 1 mhz (note 4) c in input pin capacitance 0 15 pf t f e 1 mhz notes: 1. rd /qsmd , ucs , lcs , mcs0 /pereq, mcs1 /error , lock and test /busy have internal pullups that are only acti- vated during reset. loading these pins above i ol eb 275 m a will cause the processor to enter alternate modes of operation. 2. output pins are floated using hold or once mode. 3. measured at worst case temperature and v cc with all outputs loaded as specified in the ac test conditions, and with the device in reset (resin held low). reset is worst case for i cc . 4. output capacitance is the capacitive load of a floating output pin. 5. operating conditions for 25 mhz are 0 cto a 70 c, v cc e 5.0v g 10%. 22 22
80c186ea/80c188ea, 80l186ea/80l188ea dc specifications (80l186ea/80l188ea) symbol parameter min max units conditions v cc supply voltage 2.7 5.5 v v il input low voltage for all pins b 0.5 0.3 v cc v v ih input high voltage for all pins 0.7 v cc v cc a 0.5 v v ol output low voltage 0.45 v i ol e 1.6 ma (min) v oh output high voltage v cc b 0.5 v i oh eb 1 ma (min) v hyr input hysterisis on resin 0.30 v i il1 input leakage current (except g 10 m a0v s v in s v cc rd /qsmd , ucs , lcs , mcs0 /pereq, mcs1 , lock and test ) i il2 input leakage current b 275 m av in e 0.7 v cc (rd /qsmd , ucs , lcs , mcs0 , (note 1) mcs1 , lock and test ) i ol output leakage current g 10 m a 0.45 s v out s v cc (note 2) i cc5 supply current (reset, 5.5v) 80l186ea-13 65 ma (note 3) 80l186ea-8 40 ma (note 3) i cc3 supply current (reset, 2.7v) 80l186ea-13 34 ma (note 3) 80l186ea-8 20 ma (note 3) i id5 supply current idle (5.5v) 80l186ea-13 46 ma 80l186ea-8 28 ma i id5 supply current idle (2.7v) 80l186ea-13 24 ma 80l186ea-8 14 ma i pd5 supply current powerdown (5.5v) 80l186ea-13 100 m a 80l186ea-8 100 m a i pd3 supply current powerdown (2.7v) 80l186ea-13 50 m a 80l186ea-8 50 m a c out output pin capacitance 0 15 pf t f e 1 mhz (note 4) c in input pin capacitance 0 15 pf t f e 1 mhz notes: 1. rd /qsmd , ucs , lcs , mcs0 , mcs1 , lock and test have internal pullups that are only activated during reset. loading these pins above i ol eb 275 m a will cause the processor to enter alternate modes of operation. 2. output pins are floated using hold or once mode. 3. measured at worst case temperature and v cc with all outputs loaded as specified in the ac test conditions, and with the device in reset (resin held low). 4. output capacitance is the capacitive load of a floating output pin. 23 23
80c186ea/80c188ea, 80l186ea/80l188ea i cc versus frequency and voltage the current (i cc ) consumption of the processor is essentially composed of two components; i pd and i ccs . i pd is the quiescent current that represents internal device leakage, and is measured with all inputs or floating outputs at gnd or v cc (no clock applied to the device). i pd is equal to the powerdown current and is typically less than 50 m a. i ccs is the switching current used to charge and discharge parasitic device capacitance when chang- ing logic levels. since i ccs is typically much greater than i pd ,i pd can often be ignored when calculating i cc . i ccs is related to the voltage and frequency at which the device is operating. it is given by the formula: power e v c i e v 2 c c dev c f . . . i e i cc e i ccs e v c c dev c f where: v e device operating voltage (v cc ) c dev e device capacitance f e device operating frequency i ccs e i cc e device current measuring c dev on a device like the 80c186ea would be difficult. instead, c dev is calculated using the above formula by measuring i cc at a known v cc and frequency (see table 11). using this c dev val- ue, i cc can be calculated at any voltage and fre- quency within the specified operating range. example: calculate the typical i cc when operating at 20 mhz, 4.8v. i cc e i ccs e 4.8 c 0.515 c 20 & 49 ma pdtmr pin delay calculation the pdtmr pin provides a delay between the as- sertion of nmi and the enabling of the internal clocks when exiting powerdown. a delay is required only when using the on-chip oscillator to allow the crystal or resonator circuit time to stabilize. note: the pdtmr pin function does not apply when resin is asserted (i.e., a device reset during pow- erdown is similar to a cold reset and resin must remain active until after the oscillator has stabi- lized). to calculate the value of capacitor required to pro- vide a desired delay, use the equation: 440 c t e c pd (5v, 25 c) where: t e desired delay in seconds c pd e capacitive load on pdtmr in mi- crofarads example: to get a delay of 300 m s, a capacitor value of c pd e 440 c (300 c 10 b 6 ) e 0.132 m fis required. round up to standard (available) capaci- tive values. note: the above equation applies to delay times greater than 10 m s and will compute the typical capaci- tance needed to achieve the desired delay. a delay variance of a 50% or b 25% can occur due to temperature, voltage, and device process ex- tremes. in general, higher v cc and/or lower tem- perature will decrease delay time, while lower v cc and/or higher temperature will increase delay time. table 11. c dev values parameter typ max units notes c dev (device in reset) 0.515 0.905 ma/v * mhz 1, 2 c dev (device in idle) 0.391 0.635 ma/v * mhz 1, 2 1. max c dev is calculated at b 40 c, all floating outputs driven to v cc or gnd, and all outputs loaded to 50 pf (including clkout and oscout). 2. typical c dev is calculated at 25 c with all outputs loaded to 50 pf except clkout and oscout, which are not loaded. 24 24
80c186ea/80c188ea, 80l186ea/80l188ea ac specifications ac characteristicse80c186ea25/80c186ea20/80c186ea13 symbol parameter min max min max min max units notes input clock 25 mhz (12) 20 mhz 13 mhz t f clkin frequency 0 50 0 40 0 26 mhz 1 t c clkin period 20 % 25 % 38.5 % ns 1 t ch clkin high time 10 % 10 % 12 % ns 1, 2 t cl clkin low time 10 % 10 % 12 % ns 1, 2 t cr clkin rise time 1 8 1 8 1 8 ns 1, 3 t cf clkin fall time 1 8 1 8 1 8 ns 1, 3 output clock t cd clkin to clkout delay 0 15 0 17 0 23 ns 1, 4 t clkout period 2t c 2 * t c 2 * t c ns 1 t ph clkout high time (t/2) b 5 (t/2) b 5 (t/2) b 5ns1 t pl clkout low time (t/2) b 5 (t/2) b 5 (t/2) b 5ns1 t pr clkout rise time 1 6 1 6 1 6 ns 1, 5 t pf clkout fall time 1 6 1 6 1 6 ns 1, 5 output delays t chov1 ale, s2:0 , den , dt/r , 3 20 3 22 3 25 ns 1, 4, 6, 7 bhe , (rfsh ), lock , a19:16 t chov2 mcs3:0 , lcs , ucs , pcs6:0 , 3 25 3 27 3 30 ns 1, 4, 6, 8 ncs ,rd ,wr t clov1 bhe (rfsh ), den , lock , 3 20 3 22 3 25 ns 1, 4, 6 resout, hlda, t0out, t1out, a19:16 t clov2 rd ,wr , mcs3:0 , lcs , 3 25 3 27 3 30 ns 1, 4, 6 ucs , pcs6:0 , ad15:0 (a15:8, ad7:0), ncs , inta1:0 , s2:0 t chof rd ,wr , bhe (rfsh ), dt/r , 0 25 0 25 0 25 ns 1 lock , s2:0 , a19:16 t clof den , ad15:0 (a15:8, ad7:0) 0 25 0 25 0 25 ns 1 25 25
80c186ea/80c188ea, 80l186ea/80l188ea ac specifications (continued) ac characteristicse80c186ea25/80c186ea20/80c186ea13 symbol parameter min max min max min max units notes synchronous inputs 25 mhz (12) 20 mhz 13 mhz t chis test , nmi, int3:0, 8 10 10 ns 1, 9 t1:0in, ardy t chih test , nmi, int3:0, 3 3 3 ns 1, 9 t1:0in, ardy t clis ad15:0 (ad7:0), ardy, 10 10 10 ns 1, 10 srdy, drq1:0 t clih ad15:0 (ad7:0), ardy, 3 3 3 ns 1, 10 srdy, drq1:0 t clis hold, pereq, error 10 10 10 ns 1, 9 (80c186ea only) t clih hold, pereq, error 333 ns1,9 (80c186ea only) t clis resin (to clkin) 10 10 10 ns 1, 9 t clih resin (from clkin) 3 3 3 ns 1, 9 notes: 1. see ac timing waveforms , for waveforms and definition. 2. measured at v ih for high time, v il for low time. 3. only required to guarantee i cc . maximum limits are bounded by t c ,t ch and t cl . 4. specified for a 50 pf load, see figure 13 for capacitive derating information. 5. specified for a 50 pf load, see figure 14 for rise and fall times outside 50 pf. 6. see figure 14 for rise and fall times. 7. t chov1 applies to bhe (rfsh ), lock and a19:16 only after a hold release. 8. t chov2 applies to rd and wr only after a hold release. 9. setup and hold are required to guarantee recognition. 10. setup and hold are required for proper operation. 11. t chovs applies to bhe (rfsh ) and a19:16 only after a hold release. 12. operating conditions for 25 mhz are 0 cto a 70 c, v cc e 5.0v g 10%. pin names in parentheses apply to the 80c188ea/80l188ea. 26 26
80c186ea/80c188ea, 80l186ea/80l188ea ac specifications ac characteristicse80l186ea13/80l186ea8 symbol parameter min max min max units notes input clock 13 mhz 8 mhz t f clkin frequency 0 26 0 16 mhz 1 t c clkin period 38.5 % 62.5 % ns 1 t ch clkin high time 12 % 12 % ns 1, 2 t cl clkin low time 12 % 12 % ns 1, 2 t cr clkin rise time 1 8 1 8 ns 1, 3 t cf clkin fall time 1 8 1 8 ns 1, 3 output clock t cd clkin to clkout delay 0 45 0 95 ns 1, 4 t clkout period 2 * t c 2 * t c ns 1 t ph clkout high time (t/2) b 5 (t/2) b 5ns1 t pl clkout low time (t/2) b 5 (t/2) b 5ns1 t pr clkout rise time 1 12 1 12 ns 1, 5 t pf clkout fall time 1 12 1 12 ns 1, 5 output delays t chov1 ale, lock 3 27 3 27 ns 1,4,6,7 t chov2 mcs3:0 , lcs , ucs , 332332ns1,4, pcs6:0 ,rd ,wr 6, 8 t chov3 s2:0 (den ), dt/r , 330330ns1 bhe (rfsh ), a19:16 t clov1 lock , resout, hlda, 3 27 3 27 ns 1, 4, 6 t0out, t1out t clov2 rd ,wr , mcs3:0 , lcs , 3 32 3 35 ns 1,4,6 ucs , pcs6:0 , inta1:0 t clov3 bhe (rfsh ), den , a19:16 3 30 3 30 ns 1, 4, 6 t clov4 ad15:0 (a15:8, ad7:0) 3 34 3 35 ns 1, 4, 6 t clov5 s2:0 3 38 3 40 ns 1,4,6 t chof rd ,wr , bhe (rfsh ), 027027ns1 dt/r , lock , s2:0 , a19:16 t clof den , ad15:0 (a15:8, ad7:0) 0 27 0 27 ns 1 notes: 1. see ac timing waveforms , for waveforms and definition. 2. measured at v ih for high time, v il for low time. 3. only required to guarantee i cc . maximum limits are bounded by t c ,t ch and t cl . 4. specified for a 50 pf load, see figure 13 for capacitive derating information. 5. specified for a 50 pf load, see figure 14 for rise and fall times outside 50 pf. 6. see figure 14 for rise and fall times. 7. t chov1 applies to bhe (rfsh ), lock and a19:16 only after a hold release. 8. t chov2 applies to rd and wr only after a hold release. 9. setup and hold are required to guarantee recognition. 10. setup and hold are required for proper operation. 11. t chovs applies to bhe (rfsh ) and a19:16 only after a hold release. 12. pin names in parentheses apply to the 80c188ea/80l188ea. 27 27
80c186ea/80c188ea, 80l186ea/80l188ea ac specifications ac characteristicse80l186ea13/80l186ea8 symbol parameter min max min max units notes synchronous inputs 13 mhz 8 mhz t chis test , nmi, int3:0, t1:0in, ardy 22 22 ns 1, 9 t chih test , nmi, int3:0, t1:0in, ardy 3 3 ns 1, 9 t clis ad15:0 (ad7:0), ardy, srdy, drq1:0 22 22 ns 1, 10 t clih ad15:0 (ad7:0), ardy, srdy, drq1:0 3 3 ns 1, 10 t clis hold 22 22 ns 1, 9 t clih hold 3 3 ns 1, 9 t clis resin (to clkin) 22 22 ns 1, 9 t clih resin (from clkin) 3 3 ns 1, 9 notes: 1. see ac timing waveforms , for waveforms and definition. 2. measured at v ih for high time, v il for low time. 3. only required to guarantee i cc . maximum limits are bounded by t c ,t ch and t cl . 4. specified for a 50 pf load, see figure 13 for capacitive derating information. 5. specified for a 50 pf load, see figure 14 for rise and fall times outside 50 pf. 6. see figure 14 for rise and fall times. 7. t chov1 applies to bhe (rfsh ), lock and a19:16 only after a hold release. 8. t chov2 applies to rd and wr only after a hold release. 9. setup and hold are required to guarantee recognition. 10. setup and hold are required for proper operation. 11. t chovs applies to bhe (rfsh ) and a19:16 only after a hold release. 12. pin names in parentheses apply to the 80c188ea/80l188ea. 28 28
80c186ea/80c188ea, 80l186ea/80l188ea ac specifications (continued) relative timings (80c186ea25/20/13, 80l186ea13/8) symbol parameter min max unit notes relative timings t lhll ale rising to ale falling t b 15 ns t avll address valid to ale falling (/2 t b 10 ns t plll chip selects valid to ale falling (/2 t b 10 ns 1 t llax address hold from ale falling (/2 t b 10 ns t llwl ale falling to wr falling (/2 t b 15 ns 1 t llrl ale falling to rd falling (/2 t b 15 ns 1 t rhlh rd rising to ale rising (/2 t b 10 ns 1 t whlh wr rising to ale rising (/2 t b 10 ns 1 t afrl address float to rd falling 0 ns t rlrh rd falling to rd rising (2 * t) b 5ns2 t wlwh wr falling to wr rising (2 * t) b 5ns2 t rhav rd rising to address active t b 15 ns t whdx output data hold after wr rising t b 15 ns t whdex wr rising to den rising (/2 t b 10 ns 1 t whph wr rising to chip select rising (/2 t b 10 ns 1, 4 t rhph rd rising to chip select rising (/2 t b 10 ns 1, 4 t phpl cs inactive to cs active (/2 t b 10 ns 1 t dxdl den inactive to dt/r low 0 ns 5 t ovrh once (ucs , lcs ) active to resin rising t ns 3 t rhox once (ucs , lcs ) to resin rising t ns 3 notes: 1. assumes equal loading on both pins. 2. can be extended using wait states. 3. not tested. 4. not applicable to latched a2:1. these signals change only on falling t 1 . 5. for write cycle followed by read cycle. 6. operating conditions for 25 mhz are 0 cto a 70 c, v cc e 5.0v g 10%. 29 29
80c186ea/80c188ea, 80l186ea/80l188ea ac test conditions the ac specifications are tested with the 50 pf load shown in figure 8. see the derating curves section to see how timings vary with load capacitance. specifications are measured at the v cc /2 crossing point, unless otherwise specified. see ac timing waveforms, for ac specification definitions, test pins, and illustrations. 272432 8 c l e 50 pf for all signals. figure 8. ac test load ac timing waveforms 272432 9 figure 9. input and output clock waveform 30 30
80c186ea/80c188ea, 80l186ea/80l188ea 272432 10 note: 20% v cc k float k 80% v cc figure 10. output delay and float waveform 272432 11 note: resin measured to clkin, not clkout figure 11. input setup and hold 31 31
80c186ea/80c188ea, 80l186ea/80l188ea 272432 12 notes: 1. t dxdl for write cycle followed by read cycle. 2. pin names in parentheses apply to tthe 80c188ea. figure 12. relative signal waveform 32 32
80c186ea/80c188ea, 80l186ea/80l188ea derating curves 272432 13 figure 13. typical output delay variations versus load capacitance 272432 14 figure 14. typical rise and fall variations versus load capacitance reset the processor performs a reset operation any time the resin pin is active. the resin pin is actually synchronized before it is presented internally, which means that the clock must be operating before a reset can take effect. from a power-on state, resin must be held active (low) in order to guarantee cor- rect initialization of the processor. failure to pro- vide resin while the device is powering up will result in unspecified operation of the device. figure 15 shows the correct reset sequence when first applying power to the processor. an external clock connected to clkin must not exceed the v cc threshold being applied to the processor. this is nor- mally not a problem if the clock driver is supplied with the same v cc that supplies the processor. when attaching a crystal to the device, resin must remain active until both v cc and clkout are stable (the length of time is application specific and de- pends on the startup characteristics of the crystal circuit). the resin pin is designed to operate cor- rectly using an rc reset circuit, but the designer must ensure that the ramp time for v cc is not so long that resin is never really sampled at a logic low level when v cc reaches minimum operating conditions. figure 16 shows the timing sequence when resin is applied after v cc is stable and the device has been operating. note that a reset will terminate all activity and return the processor to a known operat- ing state. any bus operation that is in progress at the time resin is asserted will terminate immediately (note that most control signals will be driven to their inactive state first before floating). while resin is active, signals rd /qsmd , ucs , lcs , mcs0 /pereq, mcs1 /error , lock , and test /busy are configured as inputs and weakly held high by internal pullup transistors. forcing ucs and lcs low selects once mode. forcing qsmd low selects queue status mode. forcing test / busy high at reset and low four clocks later enables numerics mode. forcing lock low is prohibited and results in unspecified operation. 33 33
80c186ea/80c188ea, 80l186ea/80l188ea figure 15. powerup reset waveforms 272432 15 notes: 1. clkout synchronization occurs approximately 1 (/2 clkin periods after resin is sampled low. 2. pin names in parentheses apply to the 80c188ea. 34 34
80c186ea/80c188ea, 80l186ea/80l188ea figure 16. warm reset waveforms 272432 16 notes: 1. clkout resynchronization occurs approximately 1 (/2 clkin periods after resin is sampled low. if resin is sampled low while clkout is transitioning high, then clkout will remain high for two clkin periods. if resin is sampled low while clkout is transitioning high, then clkout will not be affected. 2. pin names in parentheses apply to the 80c188ea. 35 35
80c186ea/80c188ea, 80l186ea/80l188ea bus cycle waveforms figures 17 through 23 present the various bus cycles that are generated by the processor. what is shown in the figure is the relationship of the various bus signals to clkout. these figures along with the information present in ac specifications allow the user to determine all the critical timing analysis needed for a given application. 272432-17 notes: 1. during the data phase of the bus cycle, a19/s6 is driven high for a dma or refresh cycle. 2. pin names in parentheses apply to the 80c188ea. figure 17. read, fetch and refresh cycle waveform 36 36
80c186ea/80c188ea, 80l186ea/80l188ea 272432-18 notes: 1. during the data phase of the bus cycle, a19/s6 is driven high for a dma cycle. 2. pin names in parentheses apply to the 80c188ea. figure 18. write cycle waveform 37 37
80c186ea/80c188ea, 80l186ea/80l188ea 272432 19 notes: 1. the processor drives these pins to 0 during idle and powerdown modes. 2. pin names in parentheses apply to the 80c188ea. figure 19. halt cycle waveform 38 38
80c186ea/80c188ea, 80l186ea/80l188ea notes: 272432 20 1. inta occurs one clock later in slave mode. 2. pin names in parentheses apply to the 80c188ea. figure 20. inta cycle waveform 39 39
80c186ea/80c188ea, 80l186ea/80l188ea 272432 21 note: 1. pin names in parentheses apply to the 80c188ea. figure 21. hold/hlda waveform 40 40
80c186ea/80c188ea, 80l186ea/80l188ea 272432 22 note: 1. pin names in parentheses apply to the 80c188ea. figure 22. dram refresh cycle during hold acknowledge 41 41
80c186ea/80c188ea, 80l186ea/80l188ea 272432 23 notes: 1. generalized diagram for read or write. 2. ardy low by either edge causes a wait state. only rising ardy is fully synchronized. 3. srdy low causes a wait state. srdy must meet setup and hold times to ensure correct device operation. 4. either ardy or srdy active high will terminate a bus cycle. 5. pin names in parentheses apply to the 80c188ea. figure 23. ready waveform 42 42
80c186ea/80c188ea, 80l186ea/80l188ea 80c186ea/80c188ea execution timings a determination of program exeuction timing must consider the bus cycles necessary to prefetch in- structions as well as the number of execution unit cycles necessary to execute instructions. the fol- lowing instruction timings represent the minimum execution time in clock cycle for each instruction. the timings given are based on the following as- sumptions: # the opcode, along with any data or displacement required for execution of a particular instruction, has been prefetched and resides in the queue at the time it is needed. # no wait states or bus holds occur. # all word-data is located on even-address bound- aries. (80c186ea only) all jumps and calls include the time required to fetch the opcode of the next instruction at the destination address. all instructions which involve memory accesses can require one or two additional clocks above the mini- mum timings shown due to the asynchronous hand- shake between the bus interface unit (biu) and exe- cution unit. with a 16-bit biu, the 80c186ea has sufficient bus performance to endure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time. therefore, actual program exeuc- tion time will not be substanially greater than that derived from adding the instruction timings shown. the 80c188ea 8-bit biu is limited in its performance relative to the execution unit. a sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time. therefore, actual program execution time will be substantially greater than that derived from adding the instruction timings shown. 43 43
80c186ea/80c188ea, 80l186ea/80l188ea instruction set summary function format 80c186ea 80c188ea comments clock clock cycles cycles data transfer mov e move: register to register/memory 1000100w modreg r/m 2/12 2/12 * register/memory to register 1000101w modreg r/m 2/9 2/9 immediate to register/memory 1100011w mod000 r/m data data if w e 1 1213 1213 8/16-bit immediate to register 1011w reg data data if w e 1 34 34 8/16-bit memory to accumulator 1010000w addr-low addr-high 8 8 * accumulator to memory 1010001w addr-low addr-high 9 9 * register/memory to segment register 10001110 mod0reg r/m 2/9 2/13 segment register to register/memory 10001100 mod0reg r/m 2/11 2/15 push e push: memory 11111111 mod110 r/m 16 20 register 01010 reg 10 14 segment register 000reg110 9 13 immediate 011010s0 data data if s e 01014 pusha e push all 01100000 36 68 pop e pop: memory 10001111 mod000 r/m 20 24 register 01011 reg 10 14 segment register 000reg111 (reg i 01) 8 12 popa e popall 01100001 51 83 xchg e exchange: register/memory with register 1000011w modreg r/m 4/17 4/17 * register with accumulator 10010 reg 3 3 in e input from: fixed port 1110010w port 10 10 * variable port 1110110w 8 7 * out e output to: fixed port 1110011w port 9 9 * variable port 1110111w 7 7 * xlat e translate byte to al 11010111 11 15 lea e load ea to register 10001101 modreg r/m 6 6 lds e load pointer to ds 11000101 modreg r/m (mod i 11) 18 26 les e load pointer to es 11000100 modreg r/m (mod i 11) 18 26 lahf e load ah with flags 10011111 2 2 sahf e store ah into flags 10011110 3 3 pushf e push flags 10011100 9 13 popf e pop flags 10011101 8 12 shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers. for word operations, add 4 clock cycles for all memory transfers. 44 44
80c186ea/80c188ea, 80l186ea/80l188ea instruction set summary (continued) function format 80c186ea 80c188ea comments clock clock cycles cycles data transfer (continued) segment e segment override: cs 00101110 2 2 ss 00110110 2 2 ds 00111110 2 2 es 00100110 2 2 arithmetic add e add: reg/memory with register to either 000000dw modreg r/m 3/10 3/10 * immediate to register/memory 100000sw mod000 r/m data data if s w e 01 4/16 4/16 * immediate to accumulator 0000010w data data if w e 1 3/4 3/4 8/16-bit adc e add with carry: reg/memory with register to either 000100dw modreg r/m 3/10 3/10 * immediate to register/memory 100000sw mod010 r/m data data if s w e 01 4/16 4/16 * immediate to accumulator 0001010w data data if w e 1 3/4 3/4 8/16-bit inc e increment: register/memory 1111111w mod000 r/m 3/15 3/15 * register 01000 reg 3 3 sub e subtract: reg/memory and register to either 001010dw modreg r/m 3/10 3/10 * immediate from register/memory 100000sw mod101 r/m data data if s w e 01 4/16 4/16 * immediate from accumulator 0010110w data data if w e 1 3/4 3/4 8/16-bit sbb e subtract with borrow: reg/memory and register to either 000110dw modreg r/m 3/10 3/10 * immediate from register/memory 100000sw mod011 r/m data data if s w e 01 4/16 4/16 * immediate from accumulator 0001110w data data if w e 1 3/4 3/4 * 8/16-bit dec e decrement register/memory 1111111w mod001 r/m 3/15 3/15 * register 01001 reg 3 3 cmp e compare: register/memory with register 0011101w modreg r/m 3/10 3/10 * register with register/memory 0011100w modreg r/m 3/10 3/10 * immediate with register/memory 100000sw mod111 r/m data data if s w e 01 3/10 3/10 * immediate with accumulator 0011110w data data if w e 1 3/4 3/4 8/16-bit neg e change sign register/memory 1111011w mod011 r/m 3/10 * 3/10 * aaa e ascii adjust for add 00110111 8 8 daa e decimal adjust for add 00100111 4 4 aas e ascii adjust for subtract 00111111 7 7 das e decimal adjust for subtract 00101111 4 4 mul e multiply (unsigned): 1111011w mod100 r/m register-byte 2628 2628 register-word 3537 3537 memory-byte 3234 3234 memory-word 4143 4148 * shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers. for word operations, add 4 clock cycles for all memory transfers. 45 45
80c186ea/80c188ea, 80l186ea/80l188ea instruction set summary (continued) function format 80c186ea 80c188ea comments clock clock cycles cycles arithmetic (continued) imul e integer multiply (signed): 1111011w mod101 r/m register-byte 2528 2528 register-word 3437 3437 memory-byte 3134 3234 memory-word 4043 4043 * imul e integer immediate multiply 011010s1 modreg r/m data data if s e 0 2225 22-25 (signed) 2932 2932 div e divide (unsigned): 1111011w mod110 r/m register-byte 29 29 register-word 38 38 memory-byte 35 35 memory-word 44 44 * idiv e integer divide (signed): 1111011w mod111 r/m register-byte 4452 4452 register-word 5361 5361 memory-byte 5058 5058 memory-word 5967 5967 * aam e ascii adjust for multiply 11010100 00001010 19 19 aad e ascii adjust for divide 11010101 00001010 15 15 cbw e convert byte to word 10011000 2 2 cwd e convert word to double word 10011001 4 4 logic shift/rotate instructions: register/memory by 1 1101000w modtttr/m 2/15 2/15 register/memory by cl 1101001w modtttr/m 5 a n/17 a n5 a n/17 a n register/memory by count 1100000w modtttr/m count 5 a n/17 a n5 a n/17 a n ttt instruction 000 rol 001 ror 010 rcl 011 rcr 1 0 0 shl/sal 101 shr 111 sar and e and: reg/memory and register to either 001000dw modreg r/m 3/10 3/10 * immediate to register/memory 1000000w mod100 r/m data data if w e 1 4/16 4/16 * immediate to accumulator 0010010w data data if w e 1 3/4 3/4 * 8/16-bit test e and function to flags, no result: register/memory and register 1000010w modreg r/m 3/10 3/10 * immediate data and register/memory 1111011w mod000 r/m data data if w e 1 4/10 4/10 * immediate data and accumulator 1010100w data data if w e 1 3/4 3/4 8/16-bit or e or: reg/memory and register to either 000010dw modreg r/m 3/10 3/10 * immediate to register/memory 1000000w mod001 r/m data data if w e 1 4/16 4/16 * immediate to accumulator 0000110w data data if w e 1 3/4 3/4 * 8/16-bit shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers. for word operations, add 4 clock cycles for all memory transfers. 46 46
80c186ea/80c188ea, 80l186ea/80l188ea instruction set summary (continued) function format 80c186ea 80c188ea comments clock clock cycles cycles logic (continued) xor e exclusive or: reg/memory and register to either 001100dw modreg r/m 3/10 3/10 * immediate to register/memory 1000000w mod110 r/m data data if w e 1 4/16 4/16 * immediate to accumulator 0011010w data data if w e 1 3/4 3/4 8/16-bit not e invert register/memory 1111011w mod010 r/m 3/10 3/10 * string manipulation movs e move byte/word 1010010w 14 14 * cmps e compare byte/word 1010011w 22 22 * scas e scan byte/word 1010111w 15 15 * lods e load byte/wd to al/ax 1010110w 12 12 * stos e store byte/wd from al/ax 1010101w 10 10 * ins e input byte/wd from dx port 0110110w 14 14 outs e output byte/wd to dx port 0110111w 14 14 repeated by count in cx (rep/repe/repz/repne/repnz) movs e move string 11110010 1010010w 8 a 8n 8 a 8n * cmps e compare string 1111001z 1010011w 5 a 22n 5 a 22n scas e scan string 1111001z 1010111w 5 a 15n 5 a 15n * lods e load string 11110010 1010110w 6 a 11n 6 a 11n * stos e store string 11110010 1010101w 6 a 9n 6 a 9n * ins e input string 11110010 0110110w 8 a 8n 8 a 8n * outs e output string 11110010 0110111w 8 a 8n 8 a 8n * control transfer call e call: direct within segment 11101000 disp-low disp-high 15 19 register/memory 11111111 mod010 r/m 13/19 17/27 indirect within segment direct intersegment 10011010 segment offset 23 31 segment selector indirect intersegment 11111111 mod011 r/m (mod i 11) 38 54 jmp e unconditional jump: short/long 11101011 disp-low 14 14 direct within segment 11101001 disp-low disp-high 14 14 register/memory 11111111 mod100 r/m 11/17 11/21 indirect within segment direct intersegment 11101010 segment offset 14 14 segment selector indirect intersegment 11111111 mod101 r/m (mod i 11) 26 34 shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers. for word operations, add 4 clock cycles for all memory transfers. 47 47
80c186ea/80c188ea, 80l186ea/80l188ea instruction set summary (continued) function format 80c186ea 80c188ea comments clock clock cycles cycles control transfer (continued) ret e return from call: within segment 11000011 16 20 within seg adding immed to sp 11000010 data-low data-high 18 22 intersegment 11001011 22 30 intersegment adding immediate to sp 11001010 data-low data-high 25 33 je/jz e jump on equal/zero 01110100 disp 4/13 4/13 jmp not jl/jnge e jump on less/not greater or equal 01111100 disp 4/13 4/13 taken/jmp jle/jng e jump on less or equal/not greater 01111110 disp 4/13 4/13 taken jb/jnae e jump on below/not above or equal 01110010 disp 4/13 4/13 jbe/jna e jump on below or equal/not above 01110110 disp 4/13 4/13 jp/jpe e jump on parity/parity even 01111010 disp 4/13 4/13 jo e jump on overflow 01110 000 disp 4/13 4/13 js e jump on sign 01111000 disp 4/13 4/13 jne/jnz e jump on not equal/not zero 01110101 disp 4/13 4/13 jnl/jge e jump on not less/greater or equal 01111101 disp 4/13 4/13 jnle/jg e jump on not less or equal/greater 01111111 disp 4/13 4/13 jnb/jae e jump on not below/above or equal 01110011 disp 4/13 4/13 jnbe/ja e jump on not below or equal/above 01110111 disp 4/13 4/13 jnp/jpo e jump on not par/par odd 01111011 disp 4/13 4/13 jno e jump on not overflow 01110001 disp 4/13 4/13 jns e jump on not sign 01111001 disp 4/13 4/13 jcxz e jump on cx zero 11100011 disp 5/15 5/15 loop e loop cx times 11100010 disp 6/16 6/16 loop not loopz/loope e loop while zero/equal 11100001 disp 6/16 6/16 taken/loop loopnz/loopne e loop while not zero/equal 11100000 disp 6/16 6/16 taken enter e enter procedure 11001000 data-low data-high l l e 0 15 19 l e 1 25 29 l l 1 22 a 16(n b 1) 26 a 20(n b 1) leave e leave procedure 11001001 8 8 int e interrupt: type specified 11001101 type 47 47 type 3 11001100 45 45 if int. taken/ into e interrupt on overflow 11001110 48/4 48/4 if int. not taken iret e interrupt return 11001111 28 28 bound e detect value out of range 01100010 modreg r/m 3335 3335 shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers. for word operations, add 4 clock cycles for all memory transfers. 48 48
80c186ea/80c188ea, 80l186ea/80l188ea instruction set summary (continued) function format 80c186ea 80c188ea comments clock clock cycles cycles processor control clc e clear carry 11111000 2 2 cmc e complement carry 11110101 2 2 stc e set carry 11111001 2 2 cld e clear direction 11111100 2 2 std e set direction 11111101 2 2 cli e clear interrupt 11111010 2 2 sti e set interrupt 11111011 2 2 hlt e halt 11110100 2 2 wait e wait 10011011 6 6 if test e 0 lock e bus lock prefix 11110000 2 2 nop e no operation 10010000 3 3 (ttt lll are opcode to processor extension) shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers. for word operations, add 4 clock cycles for all memory transfers. the effective address (ea) of the memory operand is computed according to the mod and r/m fields: if mod e 11 then r/m is treated as a reg field if mod e 00 then disp e 0 * , disp-low and disp- high are absent if mod e 01 then disp e disp-low sign-ex- tended to 16-bits, disp-high is absent if mod e 10 then disp e disp-high: disp-low if r/m e 000 then ea e (bx) a (si) a disp if r/m e 001 then ea e (bx) a (di) a disp if r/m e 010 then ea e (bp) a (si) a disp if r/m e 011 then ea e (bp) a (di) a disp if r/m e 100 then ea e (si) a disp if r/m e 101 then ea e (di) a disp if r/m e 110 then ea e (bp) a disp * if r/m e 111 then ea e (bx) a disp disp follows 2nd byte of instruction (before data if required) * except if mod e 00 and r/m e 110 then ea e disp-high: disp-low. ea calculation time is 4 clock cycles for all modes, and is included in the execution times given whenev- er appropriate. segment override prefix 0 0 1 reg 1 1 0 reg is assigned according to the following: segment reg register 00 es 01 cs 10 ss 11 ds reg is assigned according to the following table: 16-bit (w e 1) 8-bit (w e 0) 000 ax 000 al 001 cx 001 cl 010 dx 010 dl 011 bx 011 bl 100 sp 100 ah 101 bp 101 ch 110 si 110 dh 111 di 111 bh the physical addresses of all operands addressed by the bp register are computed using the ss seg- ment register. the physical addresses of the desti- nation operands of the string primitive operations (those addressed by the di register) are computed using the es segment, which may not be overridden. 49 49
80c186ea/80c188ea, 80l186ea/80l188ea revision history intel 80c186ea/80l186ea devices are marked with a 9-character alphanumeric intel fpo number un- derneath the product number. this data sheet up- date is valid for devices with an ``a'', ``b'', ``c'', ``d'', or ``e'' as the ninth character in the fpo number, as illustrated in figure 5 for the 68-lead plcc package, figure 6 for the 84-lead qfp (eiaj) package, and figure 7 for the 80-lead sqfp device. such devices may also be identified by reading a value of 01h, 02h, 03h from the stepid register. this data sheet replaces the following data sheets: 272019-002e80c186ea 272020-002e80c188ea 272021-002e80l186ea 272022-002e80l188ea 272307-001esb80c186ea/sb80l186ea 272308-001esb80c188ea/sb80l188ea errata an 80c186ea/80l186ea with a stepid value of 01h or 02h has the following known errata. a device with a stepid of 01h or 02h can be visually identi- fied by noting the presence of an ``a'', ``b'', or ``c'' alpha character, next to the fpo number. the fpo number location is shown in figures 5, 6, and 7. 1. an internal condition with the interrupt controller can cause no acknowledge cycle on the inta1 line in response to int1. this errata only occurs when interrupt 1 is configured in cascade mode and a higher priority interrupt exists. this errata will not occur consistantly, it is dependent on in- terrupt timing. an 80c186ea/80l186ea with a stepid value of 03h has no known errata. a device with a stepid of 03h can be visually identified by noting the presence of a ``d'' or ``e'' alpha character next to the fpo number. the fpo number location is shown in fig- ures 5, 6, and 7. 50 50

▲Up To Search▲

Price & Availability of S80L188EA13

	To Download S80L188EA13 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .